Method for attaching an integrated circuit chip to a substrate and an integrated circuit chip useful therein

ABSTRACT

An integrated circuit chip ( 10 ) includes a substrate ( 12 ), a plurality of transistors ( 16 ) provided in the substrate ( 12 ), a circuit pattern ( 14 ) provided on a top surface of the substrate ( 12 ) and a metal layer ( 42 ) comprising at least two metals in substantially eutectic proportions provided on a bottom surface of the substrate, the bottom surface of the metal layer ( 42 ) being exposed. The integrated circuit chip ( 10 ) can be attached to a farther substrate, e.g., a housing, using automated attachment techniques. The chip ( 10 ) can be attached to the housing by picking up the integrated circuit chip ( 10 ) with the metal layer ( 42 ) provided on the bottom surface thereof and placing the integrated circuit chip ( 10 ) onto a housing so the bottom surface of the integrated circuit chip ( 10 ) faces the housing with the metal layer ( 42 ) there between; and then heating the metal layer ( 42 ) to a temperature above its eutectic temperature to melt the metal layer and attach the integrated circuit chip ( 10 ) to the housing.

BACKGROUND OF THE INVENTION

1. The present invention relates to a method for attaching an integratedcircuit chip to a substrate, e.g., a housing or other next levelstructure, and an integrated circuit chip useful in such a method. Inparticular, the method is useful for attaching a high power integratedcircuit, e.g., a microwave monolithic integrated circuit (MMIC) to ahousing.

2. Integrated circuit chips can be attached to a housing using a manualeutectic attachment technique. In such a technique, a eutectic materialpreform, e.g., a gold-tin eutectic material preform, is provided betweenthe integrated circuit chip and the housing. Scrubbing is generallyrequired for the component attachment and there has been a lack ofeutectic material flow control when using a manual eutectic attachmenttechnique. In addition, most gold-tin eutectic attachments are performedwith gold-tin preforms and gold plated surfaces. The gold from the goldplated surface tends to diffuse into the preform. The resultant goldrich composition causes the rework temperature to increase.

3. Integrated circuits, e.g., high power integrated circuits, can beattached to a housing or other next level structure by an automatedassembly system using an epoxy adhesive. However, the thermalconductivity of the epoxy material which is used to attach theintegrated circuits, especially GaAs or InP integrated circuits, withthe automated assembly is about one tenth the thermal conductivity of aeutectic material, e.g., gold-tin, gold-germanium, tin-lead. Heatgenerated by high power integrated circuits, e.g., MMIC's, must beremoved to keep the operation temperature compatible with the devicelimitation. The lower thermal conductivity of the epoxy adhesive limitsthe device power or increases the operation temperature.

SUMMARY OF THE INVENTION

4. Applicants have found that there is a need to replace the low thermalconductivity adhesive with a better thermal conductivity material toenhance heat dissipation and enable high power output. There is also aneed to provide a method for attaching an integrated circuit chip to asubstrate with a method which is susceptible to automated assemblysystems.

5. The invention provides an integrated circuit chip which includes asubstrate, a plurality of transistors provided in the substrate, acircuit pattern provided on a top surface of the substrate and a metallayer comprising at least two metals in substantially eutecticproportions provided on a bottom surface of the substrate, the bottomsurface of the metal layer being exposed. The integrated circuit chipcan be attached to a further substrate, e.g., a housing, using automatedattachment techniques. The chip can be attached to the housing bypicking up the integrated circuit chip with the metal layer provided onthe bottom surface thereof and placing the integrated circuit chip,e.g., under programmed control, onto a housing so the bottom surface ofthe integrated circuit chip faces the housing with the metal layer therebetween; and then heating the metal layer to a temperature above itseutectic temperature to melt the metal layer and attach the integratedcircuit chip to the housing.

6. The metal layer can be provided on the bottom surface of theintegrated circuit chip by depositing at least one layer of each of theat least two metals and inter diffusing the at least two metals, e.g.,in an inert atmosphere to a temperature below the melting point of themetals and at or above a temperature sufficient to inter diffuse the atleast two metals. In order to economically deposit the metal layer,especially when larger thicknesses are required, e.g., up to 3.0 mil,the layer can be provided by plating at least one layer of each of theat least two metals on the bottom surface of the integrated circuit chipand inter diffusing the at least two metals. Alternatively, they can besimultaneously plated or vacuum deposited.

7. The housing is preferably made of a material, e.g., AlSiC, having acoefficient of thermal expansion close to that of the integrated circuitchip. The present invention is especially applicable to high powerintegrated circuit chips, e.g., microwave monolithic integratedcircuits, e.g., those made of GaAs or InP, which generate considerableheat which, according to the present invention, can be conducted awayfrom the chip through the eutectic material.

8. The eutectic material can be, e.g., a gold-tin eutectic. When thehousing has a gold layer on a surface to which the integrated circuitchip is attached, the eutectic layer, as deposited, can be slightly tinrich (e.g., gold:tin ratio of 78:22) in order to accommodate diffusionof gold from the housing surface to provide the eutectic proportions(80:20). A metal barrier layer, e.g., nickel for preventing diffusion ofmaterials from said integrated circuit chip into the eutectic metallayer is preferably provided on the back surface of the chip.

9. The chip is attached to the housing by heating the metal layer to atemperature above its eutectic temperature, e.g., by heating the metallayer to a temperature 30-55° C. above its eutectic temperature in aninert atmosphere. No scrubbing is required.

BRIEF DESCRIPTION OF THE DRAWINGS

10.FIG. 1 is a schematic cross-sectional view showing a non-limitativeexample of a portion of an integrated circuit chip according to thepresent invention.

11.FIG. 2 is a schematic cross-sectional view showing a non-limitativeexample of an integrated circuit chip according to the present inventionprior to its attachment to a housing or next level structure.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

12.FIG. 1 is a schematic cross-sectional view showing a portion of anintegrated circuit chip of the present invention which can be used in areworkable automated eutectic attachment system. FIG. 1 shows a portionof an integrated circuit chip 10, e.g, a high power integrated circuitchip, e.g., a microwave monolithic integrated circuit (MMIC). The chip10 includes a substrate 12, e.g., made of GaAs or InP. The chip 10 has atop side circuit 14, a portion of which is shown in FIG. 1. The chip 10also includes a plurality of transistors, one transistor 16 being shownin FIG. 1 and including a drain 18 and source 20 and a gate 22. A via 24is provided in the substrate 12. Metalization is provided on the bottomside of the chip 10. In this case, the metalization includes a titaniumadhesion layer 26, a tungsten barrier layer 28 and a gold conductivelayer 30.

13. A nickel under-plate layer 32 is provided to prevent gold leachingand eutectic flow as will be described hereinafter.

14. On the bottom surface of the nickel under-plate, a spacer layer 34,e.g., made of nickel, is provided, e.g., by plating. The function of thespacer layer 34 will be described hereinafter. The eutectic material isdeposited on the spacer 34, e.g., by plating. A photolithographicdetermined pattern (with the use of a photoresist) is used to define theplating area. In the embodiment shown in FIG. 1, the metals making upthe eutectic material are deposited in layers. More specifically, in theembodiment shown in FIG. 1, a gold metal 36 is deposited, a tin layer 38and a second gold layer 40. The layers are preferably deposited byplating, since plating can be economically used to provide thickerlayers. Other deposition techniques, e.g., vacuum deposition, can alsobe used. Vacuum deposition techniques are preferably used for providingthinner layers, e.g., for smaller components. Vacuum deposition allowsdeposition of materials which cannot be plated, e.g., gold-germanium.

15. The plated gold layer 36, tin layer 38 and gold layer 40 are theninterdiffused by heating in an inert atmosphere at a temperature lowerthan the melting temperature of the separate elements. For example, forgold and tin, the layers can be heat treated for approximately threehours at 220° C. The heat treatment causes the plated gold surface tochange color (from gold to metallic gray). The heat treatment can beconducted under any inert atmosphere, e.g., nitrogen. The meltingtemperature of the composite structure (280° C.) is higher than themelting temperature of tin (232° C.). FIG. 2 shows the chip 10 afterinterdiffusion of the metals, e.g., gold and tin, whereby the chip 10has a metal layer 42 comprising the metals, gold and tin, insubstantially eutectic proportions on a bottom surface of the chip 10.The bottom side metalization (titanium layer 26, tungsten barrier 28,gold conductive layer 30 and nickel under plate 32) on the bottom sideof the chip 10 is not shown in FIG. 2 but would cover all areas of thechip 10 except the edge set back portions 44.

16. The chip 10 with the integral eutectic metal layer 42 is picked upby an automated assembly tool, e.g., model 3500 automated assemblymachine sold by Palamar of Carlsdad, Calif. The automated assembly toolpicks up the chip 10 and places it, e.g., on a hot plate with a coveringinert gas, e.g., nitrogen. The hot plate temperature is set up to beabout 40 to 60° C. above the eutectic temperature. The attachmentsurface temperature is 30 to 55° C. above the eutectic temperature. Thecircuit pattern 14 on the component allows the automated assemblymachine to precisely pick and place the component within 0.0005 inchesof the target location.

17. The plating pattern provided by the spacer pattern 34, incombination with the thickness of the eutectic metal layer 42 isdesigned so that the volume of the eutectic metal layer 42 isapproximately equal to the volume (space) of the channels 46 formedbetween the pattern of spacers 34. The channels 46 are areas that arenot plated with spacer material 34. Since eutectic material which flowsaway from the chip 10 can short out circuits and prevent othercomponents from being placed, the channels 46 are designed toaccommodate the molten eutectic material within the perimeter of thechip 10 so that the molten eutectic material does not flow awayexcessively from the chip 10. The spacers 34 are provided in the areasthat have a need for thermal conduction. The spacers 34 can also controlthe bond line minimum thickness and can support all bonding pads.

18. The housing or next level structure to which the chip 10 is attachedis preferably made of a material, e.g., AlSiC, having a coefficient ofthermal expansion close to that of the integrated circuit chip. In thecase of MMIC chips made of GaAs or InP, it is preferred that thematerial of the housing have a coefficient of thermal expansion lessthan 10 PPM/° C. Since the housing surface would typically have a goldlayer thereon, it is preferred that the eutectic metal layer 42, asdeposited, is made slightly gold deficient, i.e., slightly tin rich,e.g., gold:tin ratio of 78:22, in order to accommodate diffusion of goldfrom the housing surface to provide the eutectic proportions (80:20).This will ensure that reworking can be conducted at the eutectictemperature.

19. The under plate layer 32, e.g., nickel, prevents the componentsbackside gold plating 30 from diffusing or dissolving in the molteneutectic material during the attachment process.

20. While the metal layer 42 has been described as a gold-tin eutecticmetal layer, other materials can be used as long as the material has amelting point within the range of about 50 to 400° C. Since it ispreferable that the material have a limited, precise melting point,eutectic materials are preferred, e.g., gold-tin, gold-germanium,tin-lead.

21. The thickness of the metal layer 42 depends on the type of chip, butis preferably in the range of 0.1 to 3.0 mil, more preferably 0.5 to 1.0mil, especially in the case of MMIC chips. While minimum eutecticmaterial thickness can minimize thermal impedance, the volume of theeutectic material must be sufficient to fill the space between twopoorly matched surfaces. A 0.5 mil thick metal layer 42 should besufficient for surface roughness of up to 40 micro inches.

22. It is preferable that picking up of the integrated circuit chip 10with the metal layer 42 provided thereon and placing the integratingcircuit chip 10 onto a housing or other next level structure beaccomplished using an automated assembly machine under programmedcontrol. Such automated assembly machines are known in the art.Satisfactory results have been obtained using a Palomar Model 3500machine. Applicants have previously used the Palomar Model 3500 foraccurate placement of chips using epoxy adhesive. Applicants havemodified the Palomar Model 3500 machine to operate at highertemperatures to achieve attachment using the eutectic metal layer. Whilethe Palomar Model 3500 is able to apply scrubbing action to thecomponents, applicants have found that component surface damage, e.g.,scratches, can occur. Therefore, scrubbing is neither recommended norrequired.

We claim:
 1. A method for attaching an integrated circuit chip to asubstrate, comprising the steps of: providing an integrated circuitchip; providing a metal layer comprising at least two metals insubstantially eutectic proportions on a bottom surface of the integratedcircuit chip; picking up the integrated circuit chip with the metallayer provided on the bottom surface thereof and placing the integratedcircuit chip onto a substrate so the bottom surface of the integratedcircuit chip faces the substrate with the metal layer there between; andheating the metal layer to a temperature above its eutectic temperatureto melt the metal layer and attach the integrated circuit chip to thesubstrate.
 2. A method according to claim 1 , wherein the step ofproviding the metal layer comprising at least two metals insubstantially eutectic proportions on the bottom surface of theintegrated circuit chip comprises the steps of depositing at least onelayer of each of the at least two metals and inter-diffusing the atleast two metals.
 3. A method according to claim 2 , wherein the step ofinter diffusing the at least two metals comprises heating the at leastone layer of each of the at least two metals in an inert atmosphere to atemperature below the melting point of the metals and at or above atemperature sufficient to inter diffuse the at least two metals.
 4. Amethod according to claim 2 , wherein the step of depositing at leastone layer of each of the at least two metals comprises plating at leastone layer of each of the at least two metals on the bottom surface ofthe integrated circuit chip.
 5. A method according to claim 2 , whereinthe step of depositing at least one layer of each of the at least twometals comprises vacuum depositing at least one layer of each of the atleast two metals on the bottom surface of the integrated circuit chip.6. A method according to claim 1 , wherein the step of providing themetal layer comprising at least two metals in substantially eutecticproportions on the bottom surface of the integrated circuit chipcomprises simultaneously depositing the at least two metals insubstantially eutectic proportions.
 7. A method according to claim 1 ,wherein the substrate is a housing.
 8. A method according to claim 7 ,wherein the housing is made of a material having a coefficient ofthermal expansion close to that of the integrated circuit chip, andwherein the housing has a gold layer on a surface to which theintegrated circuit chip is attached.
 9. A method according to claim 8 ,wherein the step of providing the metal layer comprising at least twometals in substantially eutectic proportions on the bottom surface ofthe integrated circuit chip comprises depositing gold and tin insubstantially eutectic proportions on the bottom surface of theintegrated circuit chip.
 10. A method according to claim 9 , wherein thestep of providing the metal layer comprising at least two metals insubstantially eutectic proportions on the bottom surface of theintegrated circuit chip comprises the steps of depositing at least onelayer of each of gold and tin and inter diffusing the layers of gold andtin.
 11. A method according to claim 10 , wherein, in the step ofdepositing at least one layer of each of gold and tin, a weight ratio ofgold:tin is about 78:22.
 12. A method according to claim 1 , wherein thestep of providing the metal layer comprising at least two metals insubstantially eutectic proportions on the bottom surface of theintegrated circuit chip comprises depositing gold and tin insubstantially eutectic proportions on the bottom surface of theintegrated circuit chip.
 13. A method according to claim 12 , whereinthe step of providing the metal layer comprising at least two metals insubstantially eutectic proportions on the bottom surface of theintegrated circuit chip comprises the steps of depositing at least onelayer of each of gold and tin and inter diffusing the layers of gold andtin.
 14. A method according to claim 1 , wherein the step of providingthe metal layer comprising at least two metals in substantially eutecticproportions on the bottom surface of the integrated circuit chipcomprises depositing the at least two metals by plating and wherein athickness of the metal layer is 0.1-3.0 mil.
 15. A method according toclaim 1 , wherein the step of providing the metal layer comprising atleast two metals in substantially eutectic proportions on the bottomsurface of the integrated circuit chip comprises depositing the at leasttwo metals by plating and wherein a thickness of the metal layer isabout 0.5-1.0 mil.
 16. A method according to claim 1 , wherein the stepof heating the metal layer to a temperature above its eutectictemperature comprises heating the metal layer to a temperature 30-55°C.above its eutectic temperature.
 17. A method according to claim 1 ,wherein the step of heating the metal layer to a temperature above itseutectic temperature comprises heating the metal layer to a temperature30-55° C. above its eutectic temperature in an inert atmosphere.
 18. Amethod according to claim 1 , wherein the step of providing the metallayer comprising at least two metals in substantially eutecticproportions on the bottom surface of the integrated circuit chipcomprises providing the metal layer on a barrier layer for preventingdiffusion of materials from said integrated circuit chip into the metallayer.
 19. A method according to claim 1 , wherein the barrier layercomprises nickel.
 20. A method according to claim 1 , wherein theintegrated circuit chip is a high power integrated circuit chip.
 21. Amethod according to claim 20 , wherein the high power integrated circuitchip comprises GaAs or InP and the substrate comprises AlSiC.
 22. Amethod according to claim 20 , wherein the high power integrated circuitchip is a microwave monolithic integrated circuit chip.
 23. A methodaccording to claim 1 , wherein the step of picking up the integratedcircuit chip with the metal layer provided on the bottom surface thereofand placing the integrated circuit chip onto the substrate isaccomplished using an automated assembly machine.
 24. A method accordingto claim 1 , wherein the step of picking up the integrated circuit chipwith the metal layer provided on the bottom surface thereof and placingthe integrated circuit chip onto the substrate is done under programmedcontrol.
 25. An integrated circuit chip, comprising a substrate, aplurality of transistors provided in the substrate, a circuit patternprovided on a top surface of the substrate and a metal layer comprisingat least two metals in substantially eutectic proportions provided on abottom surface of the substrate, wherein a bottom surface of the metallayer is exposed.
 26. An integrated circuit chip according to claim 25 ,wherein the at least two metals in substantially eutectic proportionsare plated on the substrate and the metal layer has a thickness of0.1-3.0 mil.
 27. An integrated circuit chip according to claim 25 ,wherein the metal layer comprises a layer containing gold and tin insubstantially eutectic proportions.
 28. An integrated circuit chipaccording to claim 25 , wherein the metal layer comprises a layercontaining gold and tin having a weight ratio of gold:tin of about78:22.
 29. An integrated circuit chip according to claim 25 , whereinthe metal layer comprises a layer containing gold and tin having aweight ratio of gold:tin in a range of 76:24-80:20.
 30. An integratedcircuit chip according to claim 25 , wherein the metal layer comprisesat least one layer of gold and at least one layer of tin.
 31. Anintegrated circuit chip according to claim 25 , wherein a thickness ofeach of the at least one layer of gold and at least one layer of tinprovide a weight ratio of gold:tin in a range of 76:24-80:20.